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ltc1699 series 1 , ltc and lt are registered trademarks of linear technology corporation. n fully compliant with intel 5-bit mobile (ltc1699-80) and desktop vrm8.4 (ltc1699-81) and vrm9.0 (ltc1699-82) vid specifications n precision 0.35% programmable resistor divider for use with 0.8v referenced dc/dc converters n two different divider settings can be stored using a 2-wire smbus serial interface (rev 1.1) n built-in safeguards minimize misprogramming due to bus conflicts n three open-drain pins (cpu_on, io_on, clk_on) and a global control pin (vron)to shutdown or soft-start 3 dc/dc converters simultaneously n pgood pin and 50 m s pgood timer n available in msop-8 and ssop-16 package amd athlon is a trademark of advanced micro devices, inc. pentium is a registered trademark of intel corporation. intel speedstep is a trademark of intel corporation. the ltc ? 1699-80, ltc1699-81 and ltc1699-82 are pre- cision ( 0.35% max), digitally programmed resistor di- viders that comply with intel 5-bit mobile (ltc1699-80), desktop vrm8.4 (ltc1699-81) and vrm9.0 (ltc1699-82) vid specifications. each ic can switch the output of a dc/dc converter between two set voltages. a digital input pin, sel, selects one of two divider settings stored into registers via a 2-wire smbus interface. the smbus interface uses write word protocol to setup the registers and to turn the dc/dc converters on or off. read word protocol is used to verify register contents and to return the on/off status of the converters. the ltc1699-80, ltc1699-81 and ltc1699-82 incorporate safeguards against errors due to bus conflicts. three open-drain n-channel outputs (cpu_on, io_on and clk_on) are provided to turn dc/dc converter sup- plies on or off via their run/ss inputs. a global control pin, vron is used to turn the converters on or off simulta- neously. an internal timer pulls the pgood pin low for 50 m s if the divider setting changes or the converters are turned on via the smbus and the vron pin. n intel desktop pentium ? iii power supply n intel mobile pentium ? power supply with intel speedstep tm technology n desktop amd athlon tm power supply n software programmable remote power supply n power supplies with voltage margining smbus vid voltage programmers 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 cpu_on io_on clk_on pgood fb vron scl sel sda vron scl sel sda sense v cc u1 ltc1699-81 m1 m2 l1, 1 h c1 10 f 25v c1, c2, c3, c4, c9: taiyo yudan c5: sanyo c10, c11: panasonic, spcl. poly. d1: cmdsh-3 d2: diodes inc., b340a l1: toko, 919as-1ron m1: si4884dy m2: si4874dy c2 10 f 25v c3 10 f 25v c9 22 f 6.3v c4 10 f 25v c5 10 f 35v alum d2 d1 v in 5vdc 5 3 4 1 nc 2 nc 7 nc 11 gnd 14 gnd 15 8 13 9 10 6 12 16 run/ss pgood v rng fcb i th sgnd i on v fb boost tg sw pgnd bg intv cc v in extv cc u2 ltc1778 1699 ta05 v in 5v to 20v r4 10k r3 1 r5 715k, 1% r2, 11k c7 0.22 f c15 220pf c12 0.1 f c19, 0.01 f c8 0.01 f + c11 180 f 4v gnd gnd 5v v out 2.5v at 10a + c10 180 f 4v + c18 2200pf c14, 0.1 f c8, 0.01 f r1 39k r9 100k pgood c13 4.7 f 6.3v smbus controlled high efficiency dc/dc converter applicatio s u features typical applicatio u descriptio u
ltc1699 series 2 order part number ms8 part marking t jmax = 125 c, q ja = 200 c/w consult factory for parts specified with wider operating temperature ranges. ltpv ltpw lttb ltc1699ems8-80 ltc1699ems8-81 ltc1699ems8-82 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 2.7v v cc 5.5v (notes 3, 4) unless otherwise stated. symbol parameter conditions min typ max units v cc operating supply voltage range 2.7 5.5 v i cc supply current cpu_on, io_on, clk_on, pgood pins are open l 350 m a r fb-sense resistance between sense and fb ltc1699-80, ltc1699-82 l 71013 k w ltc1699-81 l 14 20 26 k w de divider error all divider settings l C 0.35 0.35 % v ih scl, sda input high voltage l 2.1 v v il scl, sda input low voltage l 0.8 v v ih sel, vron input high voltage 1.3 2.0 v v il sel, vron input low voltage l 0.8 1.3 v v hyst sel, vron hysteresis 50 mv v ol sda, cpu_on, io_on, clk_on i = 3ma l 0.4 v output low voltage i in scl, sda, sel, vron input current sda not acknowledging, 0 v pin 5.5v, v pin = 5.5v for vron only l 10 m a supply voltage (v cc ) ................................................. 7v all pins ........................................................C 0.3v to 7v operating temperature range (note 2) ................................ C40 c t a 85 c junction temperature ........................................... 125 c storage temperature ...................... -65 c t a 150 c lead temperature (soldering, 10 sec).................. 300 c order part number gn part marking 169980 169981 169982 LTC1699EGN-80 ltc1699egn-81 ltc1699egn-82 t jmax = 125 c, q ja = 130 c/w 1 2 3 4 5 6 7 8 top view gn package 16-lead plastic ssop 16 15 14 13 12 11 10 9 sel nc sda scl vron pgood nc cpu_on v cc gnd gnd fb sense nc clk_on io_on 1 2 3 4 sel sda scl pgood 8 7 6 5 v cc gnd fb sense top view ms8 package 8-lead plastic msop
ltc1699 series 3 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 2.7v v cc 5.5v (notes 3, 4) unless otherwise stated. symbol parameter conditions min typ max units i sk1 sda, pgood, cpu_on, io_on, 0 v pin 2.7v l 51960 ma clk_on sink current at v cc = 2.7v i sk2 sda, pgood, cpu_on, io_on, 0 v pin 5.5v l 35 65 150 ma clk_on sink current at v cc = 5.5v i lkg pgood, cpu_on, io_on, 0 v pin 5.5v l 2 m a clk_on leakage current i pu vron pull-up current v pin = 0 l C1 C 2.5 C 7 m a timing (note 5) f smb smbus operating frequency l 10 100 khz t buf bus free time between stop/start l 4.7 m s t hd:sta hold time after (repeated) start l 4.0 m s t su:sta repeated start setup time l 4.7 m s t su:sto stop condition setup time l 4.0 m s t hd:dat data hold time l 300 ns t su:dat data setup time l 250 ns t low clock low period l 4.7 m s t high clock high period l 4.0 m s t f scl, sda fall time 0.9v cc to 0.65v l 300 ns t r scl, sda rise time 0.65v to 2.25v l 1000 ns t ssh sel to sense high (note 6) toggle sel to switch from min v out to max v out , 500 ns vfb = 0.8v t ssl sel to sense low (note 6) toggle sel to switch from max v out to min v out , 500 ns vfb = 0.8v t spl sel toggling to pgood low toggle sel to select new code l 160 500 ns c l = 100pf, 10k w pull-up, s2 in figure 1 t ph stop bit to cpu_on, io_on c l = 100pf, 10k w pull-up, s2 in figure 1 l 2 m s or clk_on high (note 7) t pl stop bit to cpu_on, io_on c l = 0.1 m f, 10k w pull-up, s1 in figure 1 l 20 50 m s or clk_on low (note 7) t ppl stop bit to pgood low (note 6) c l = 100pf, 10k w pull-up, s2 in figure 1 l 250 ns t vh vron high to cpu_on, io_on c l = 100pf, 10k w pull-up, s2 in figure 1 l 2 m s or clk_on high t vl vron low to cpu_on, io_on, c l = 0.1 m f, 10k w pull-up, s1 in figure 1 l 50 m s clk_on low t vpl vron low to pgood low c l = 100pf, 10k w pull-up, s2 in figure 1 l 130 500 ns t pgl pgood low duration c l = 100pf, 10k w pull-up, s2 in figure 1 l 30 50 70 m s note1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc1699-80e, ltc1699-81e and ltc1699-82e are guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise specified. note 4: all typical numbers are given for v cc = 5v and t a = 25 c. note 5: these parameters are guaranteed by design and are not tested in production. smbus timing is referenced to v il and v ih levels. note 6: dominated by the switching regulator. the delay due to the ltc1699-80, ltc1699-81 or ltc1699-82 is typically 500ns. note 7: measured from the rising edge of sda during data high acknowledgement.
ltc1699 series 4 typical perfor a ce characteristics uw supply current vs supply voltage supply current vs temperature resistance between sense and fb pins vs temperature (ltc1699-81) scl, sda, sel and vron input high and low voltage vs temperature scl, sda, sel and vron input high and low voltage vs supply voltage scl, sda, sel and vron hysteresis vs temperature scl, sda, sel and vron hysteresis vs supply voltage sda, cpu_on, io_on, clk_on output low voltage vs temperature v cc (v) 1.5 supply current ( a) 1699 g01 350 300 250 200 150 100 50 0 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 t a = 25 c temperature ( c) supply current ( a) 1699 g02 300 250 200 150 100 50 0 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 5.5v v cc = 2.7v temperature ( c) r sense (k ) 1699 g03 20.08 20.06 20.04 20.02 20.00 19.98 19.96 19.94 19.92 19.90 19.88 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 2.7v to 5.5v temperature ( c) input high and low voltage (v) 1699 g04 1.40 1.35 1.30 1.25 1.20 1.15 1.10 ?5 ?5 ?5 5 25 45 65 85 105 125 input high, v cc = 5.5v input low, v cc = 5.5v input high, v cc = 2.7v input low, v cc = 2.7v supply voltage (v) input high and low voltage (v) 1699 g05 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 input high t a = 25 c input low temperature ( c) hysteresis (v) 1699 g06 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 5.5v v cc = 2.7v supply voltage (v) hysteresis (v) 1699 g07 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 t = 25 c temperature ( c) output low voltage (v) 1699 g08 0.25 0.20 0.15 0.10 0.05 0 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 2.7v i pin = 3ma v cc = 5.5v temperature ( c) r sense (k ) 1699 g18 10.08 10.06 10.04 10.02 10.00 9.98 9.96 9.94 9.92 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 2.7v to 5.5v resistance between sense and fb pins vs temperature (ltc1699-80, ltc1699-82)
ltc1699 series 5 typical perfor a ce characteristics uw scl, sda and sel input current vs temperature temperature ( c) input current (na) 1699 g09 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ?5 ?5 ?5 5 25 45 65 85 105 125 scl pin sel pin sda pin v cc = 5.5v v pin = 5.5v sda, pgood, cpu_on, io_on, clk_on sink current vs temperature pgood, cpu_on, io_on, clk_on leakage current vs temperature vron pull-up current vs temperature vron pull-up current vs supply voltage power good low duration vs temperature ltc1699-80 divider error vs temperature ltc1699-81 divider error vs temperature ltc1699-82 divider error vs temperature temperature ( c) sink current (ma) 1699 g10 80 70 60 50 40 30 20 10 0 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 5.5v, i sk2 v cc = 2.7v, i sk1 temperature ( c) leakage current (na) 1699 g11 7 6 5 4 3 2 1 0 ?0 ?0 ?0 0 20 40 60 80 100 120 v pin = 5.5v temperature ( c) vron pull-up current ( a) 1699 g12 2.50 2.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 5.5v v cc = 2.7v supply voltage (v) 1.5 ? vron pull-up current ? ( a) 1699 g013 3.0 2.5 2.0 1.5 1.0 0.5 0 2.5 3.5 4.5 5.5 6.5 t a = 25 c v ron = 0v temperature ( c) divider error (%) 1699 g15 0.05 0 0.05 0.10 0.15 0.20 ?5 35 ?5 5 25 45 65 85 105 125 v cc = 2.7v (minimum v cc ) code 31 code 15 code 16 code 0 temperature ( c) divider error (%) 1699 g16 0.25 0.20 0.15 0.10 0.05 0 0.05 0.10 0.15 0.20 ?5 35 ?5 5 25 45 65 85 105 125 v cc = 2.7v (minimum v cc ) code 15 code 31 code 0 code 16 temperature ( c) power good low duration ( s) 1699 g14 52.0 51.5 51.0 50.5 50.0 49.5 49.0 ?0 ?0 ?0 0 20 40 60 80 100 120 v cc = 5.5v v cc = 2.7v temperature ( c) divider error (%) 1699 g17 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0.02 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 2.7v (minimum v cc ) code 31 code 15 code 16 code 0
ltc1699 series 6 note: pin numbers apply to 16-lead ssop packages. sel (pin 1): register select input. a ttl compatible logic input pin that is used to select 1 of 2 resistor divider settings. sel selects the setting in register 0 if pulled low and the setting in register 1 if pulled high. nc (pin 2): not connected. sda (pin 3): smbus data input/output. sda is a high impedance input when address, command or data bits are shifted in. it is an open drain, n-channel output when acknowledging or sending data back to the microproces- sor during read-back. it requires a pull-up resistor or current source to v cc . scl (pin 4): smbus clock input. data at the sda pin is latched into the ltc1699 at the rising edge of the clock and is shifted out of the sda pin at the falling edge of the clock. scl is a high impedance input pin. it is driven by the open collector output of a microprocessor and requires a pull- up resistor or current source to v cc . vron (pin 5): global control input. this ttl compatible input pin is pulled up internally by a 2.5 m a current source. pulling vron low forces the open drain output pins (cpu_on, io_on, clk_on and pgood) to pull to ground. if the ltc1699-80, ltc1699-81 or ltc1699-82 is pro- grammed to turn on dc/dc converters, pulling vron high three-states the cpu_on, io_on and clk_on pins and allows the dc/dc converters to soft-start. pgood (pin 6): power good output. this open drain output is pulled low for 50 m s each time the ltc1699-80, ltc1699-81 or ltc1699-82 turns on the dc/dc convert- ers or sel is toggled to select a new code. pgood may be connected to the fcb input of an ltc dc/dc converter to force the converter into continuous mode operation. this reduces the time needed for the converter output to settle to a lower output voltage under light load conditions if the sel pin is toggled. nc (pin 7): not connected. cpu_on (pin 8): cpu dc/dc converter control. open drain output, usually connected to the run/ss pin of a dc/ dc converter that generates the cpu core supply. it pulls low to shut down the converter or becomes a high imped- ance state to allow the converter to soft-start. io_on (pin 9): i/o dc/dc converter control. open drain output, normally connected to the run/ss pin of the dc/ dc converter that generates the i/o supply. it pulls low to shut down the converter or becomes a high impedance state to allow the converter to soft-start. clk_on (pin 10): clock dc/dc converter control. open drain output, optionally connected to the run/ss pin of the dc/dc converter that generates the supply for the clock buffer. it pulls low to shut down the converter or becomes a high impedance state to allow the converter to soft-start. nc (pin 11): not connected. sense (pin 12): sense input. upper terminal of the resistor divider that is connected directly to the output voltage being regulated. fb (pin 13): feedback input. center tap of the divider that is connected to the feedback pin of an ltc 0.8v referenced dc/dc converter. gnd (pin 14): ground. connect to regulator signal ground. gnd (pin 15): divider ground. short to pin 14. v cc (pin 16): positive supply. 2.7v v cc 5.5v. bypass this pin to ground with a 0.1 m f ceramic capacitor. pi fu ctio s uuu
ltc1699 series 7 fu ctio al block diagra uu w mux/decoder setup read- back r1* ltc1699-80, r1 = 10k ltc1699-81, r1 = 20k ltc1699-82, r1 = 10k * gnd fb sense sel 5 r2 5 v cc sda scl 5 3 latch control smbon dcon 1699 fbd 2.5 a pgood vron cpu_on io_on clk_on 5 5 command latch and decoder register control logic on off on/off state machine 50 s timer converter control logic register 0 register 1 power-on reset smbus interface test circuit + cpu_on or io_on or clk_on or pgood fb sense vron gnd 1699 f01 sel sda scl v cc vron sel sda scl 10k s1 5v 5v 0.1 f s2 0.8v 100pf figure 1. load for timing tests
ltc1699 series 8 ti i g diagra s w u w slave address command code data low data high 1 1 scl sda 11 1 xxxxx xxx xxx r/w ack vid4 vid3 vid0 vid2 vid1 c7 c6 c5 000 23456789 10111213141516171819202122232425262728293031323334353637 p s r/w ack vid4 vid3 vid0 vid2 vid1 ack vid4 vid3 vid0 vid1 vid2 ack ack slave address slave address command code data low data high 1 1 scl sda note 1: s = start condition, p = stop condition note 2: c7, c6, c5 = 001 for setup, 010 for read-back, 000 for on and 011 for off 1699 td01 11 1 xxxxx ack c7 c6 c5 000 1 1 rd 11000 0 0 23456789 101112131415161718 smbus write word protocol, with smbus address = 1110001b, command byte = 001x xxxb, data low = 0100 1xxxb, data high = 0101 1xxxb smbus read word protocol, with smbus address = 1110001b, command byte = 010x xxxb, data low = 0100 1000b, data high = 0101 1000b 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 p s ack s vid4 vid3 vid0 vid1 vid2 ack dcon 0 0 dcon ack operating sequences
ltc1699 series 9 ti i g diagra s w u w t buf t low t high t r t f t hd:sta t hd:dat sda scl t su:dat t su:sta t su:sto stop 1699 td02 start start stop t hd:sta 1699 td03 t ph t spl t vl t ssh t pl t ppl t vpl t pgl t vh t ssl 90% 10% note: timing relative to the stop bit (p) is measured from the rising edge of sda see table 1 for v min and v max sense voltages t pgl t pgl scl p stop 2nd on protocol 2nd off protocol smbon dcon vron cpu_on io_on clk_on v sense (v ref = 0.8v) sel sda pgood p 1.3v 1.3v 1.3v 1.3v 0.7v v max v min 0v 0v timing for smbus interface clk_on, io_on, clk_on, pgood timing
ltc1699 series 10 applicatio s i for atio wu u u in general, adjustable dc/dc converters regulate the output voltage by dividing it down with a resistor divider and comparing the result against a precision reference voltage (v ref ). as shown in the block diagram, the ltc1699-80, ltc1699-81 and ltc1699-82 are variable resistor dividers, which are programmed through a 2-wire smbus interface. they are specifically designed to sim- plify the implementation of a voltage regulator module (vrm) in both portable and desktop computers. two 5-bit divider settings can be programmed into regis- ter 0 and register 1 using the smbus interface. the microprocessor selects one of these settings using the ttl compatible sel pin to control a 10:5 multiplexer (mux). the precision 0.35% divider is intended to set the table 1. dc/dc converter output voltage for v ref = 0.8v vid4 vid3 vid2 vid1 vid0 ltc1699-80 ltc1699-81 ltc1699-82 00000 2.000v 2.05v 1.850v 00001 1.950v 2.00v 1.825v 00010 1.900v 1.95v 1.800v 00011 1.850v 1.90v 1.775v 00100 1.800v 1.85v 1.750v 00101 1.750v 1.80v 1.725v 00110 1.700v 1.75v 1.700v 00111 1.650v 1.70v 1.675v 01000 1.600v 1.65v 1.650v 01001 1.550v 1.60v 1.625v 01010 1.500v 1.55v 1.600v 01011 1.450v 1.50v 1.575v 01100 1.400v 1.45v 1.550v 01101 1.350v 1.40v 1.525v 01110 1.300v 1.35v 1.500v 01111 1.250v 1.30v 1.475v 10000 1.275v 3.50v 1.450v 10001 1.250v 3.40v 1.425v 10010 1.225v 3.30v 1.400v 10011 1.200v 3.20v 1.375v 10100 1.175v 3.10v 1.350v 10101 1.150v 3.00v 1.325v 10110 1.125v 2.90v 1.300v 10111 1.100v 2.80v 1.275v 11000 1.075v 2.70v 1.250v 11001 1.050v 2.60v 1.225v 11010 1.025v 2.50v 1.200v 11011 1.000v 2.40v 1.175v 11100 0.975v 2.30v 1.150v 11101 0.950v 2.20v 1.125v 11110 0.925v 2.10v 1.100v 11111 0.900v 2.00v 1.075v
ltc1699 series 11 applicatio s i for atio wu u u output voltage of a dc/dc converter that generates the cpu core supply voltage. its programmable ratios (see table 1) are designed for 0.8v-referenced converters such as the ltc1628, ltc1702, ltc1735 and ltc1778 and comply with the intel 5-bit desktop (vrm8.4 for ltc1699-81 and vrm9.0 for ltc1699-82) and 5-bit mobile vid codes. on power-up, the outputs of both registers are internally set to 11111b. the ltc1699-80, ltc1699-81 and ltc1699-82 provide three pins, cpu_on, io_on, and clk_on to (optionally) control three dc/dc converters that generate the cpu, i/o and clock buffer v cc voltages in a vrm. these open drain, n-channel output pins usually connect to the run/ss pins of the converters and pull low to shut down the converters or become a high impedance state to allow the converters to soft-start. the pgood pin is driven from an internal timer that pulls pgood low for 50 m s typical whenever the resistor divider setting is changed or the converters are allowed to soft- start. over the entire temperature and supply voltage range, the timer low period is 70 m s max which meets the 100 m s max converter output settling time specified by intel. the pgood pin, if tied to the fcb pin of an ltc dc/ dc converter, reduces the time needed for the converter output to decrease to a lower voltage under light load conditions by forcing the converter into continuous mode for 50 m s. the ttl compatible vron input pin and the output of the internal on/off state machine (smbon) control the state of the cpu_on, io_on, clk_on and pgood pins. smbon is accessed using smbus protocols and must be pro- grammed to a high state before the converters can turn on. the smbus protocols (see figure 2) incorporate safe- guards against errors caused by bus conflicts. resistor divider the resistor divider is designed specifically for dc/dc converters, such as the ltc1628, ltc1702, ltc1735, ltc1778 and ltc1929 with a reference voltage of 0.8v. it consists of a fixed resistor, r fb1 connected between the sense and fb pins and a variable resistor, r fb2 , con- nected between the fb and gnd pins. the sense and fb pins are tied to the output and feedback nodes of the dc/ dc converter respectively. the output of the dc/dc con- verter is given by: v out = v ref ? (r fb2 +r fb1 )/r fb2 where v ref is the internal reference voltage of the con- verter. each resistor has a tolerance of 30% but the ratio, (r fb2 +r fb1 )/r fb2 , is specified to within 0.35% over temperature. the error budget for the dc/dc converter output voltage must include the 0.35% ratio tolerance and the tolerance in v ref . the value of r fb1 is fixed and r fb2 is changed to vary the divider setting. the value of r fb2 for any divider setting can be calculated from the above equation, assuming that r fb1 = 10k w for the ltc1699-80 and ltc1699-82 and 20k w for the ltc1699-81. table 1 shows the output voltage of a dc/dc converter (v ref = 0.8v) for all 32 settings of the resistor divider. the divider setting is determined by the outputs (vid0-vid4) of the register selected by the sel pin. smbus interface the smbus interface uses two wires: sda and scl. data to the ltc1699-80, ltc1699-81 or ltc1699-82, is latched at the rising edge of the scl clock input and shifted out at the falling edge. the v il and v ih logic threshold voltages of the sda and scl pins are 0.8v and 2.1v respectively and comply with rev 1.1 version of the intel system management bus specifications. the write word and read word protocols (figure 2) share three common features. first, the 7-bit slave address for both protocols is internally hardwired to 1110 001b = e2h. a single r/w bit follows the slave address. this bit is low for data transfer from the microprocessor to the ltc1699- 80, ltc1699-81 or ltc1699-82 and high for transfers in the opposite direction. second, the ltc1699-80, ltc1699-81 and ltc1699-82 decode only the three most significant bits of the 8-bit command code. table 2 shows the four valid combina- tions. all other combinations are ignored. third, the data low and data high bytes correspond to registers 0 and 1 respectively. in write word protocol with c7 = c6 = 0, c5 = 1, the five most significant bits (vid0- vid4) of these bytes specify a resistor divider setting.
ltc1699 series 12 applicatio s i for atio wu u u table 2. ltc1699-80, ltc1699-81 and ltc1699-82 command bits c7 c6 c5 command protocol 0 0 0 on write word 0 1 1 off write word 0 0 1 setup write word 0 1 0 read-back read word write word protocol each write word protocol (figure 2) begins with a start bit (s) and ends with a stop bit (p). as shown in the timing diagram the start and stop bits are defined as high to low and low to high transitions respectively, while scl is high. in between the start and stop bits, the microprocessor transmits four bytes to the ltc1699-80, ltc1699-81 or ltc1699-82. these are the address byte, an 8-bit com- mand code and two data bytes. the ltc1699-80, ltc1699-81 and ltc1699-82 sample each bit at the rising edges of the scl clock. when the microprocessor issues a start bit, all the slave devices on the bus, including the ltc1699-80, ltc1699-81 or ltc1699-82 clock in the address byte, which consists of a 7-bit slave address and the r/w bit (set to 0). if the slave address from the microprocessor does not match the internal hardwired address, the ltc1699-80, ltc1699-81 or ltc1699-82 returns to an idle state and waits for the next start bit. if the slave address matches, the ltc1699-80, ltc1699-81 or ltc1699-82 acknowl- edges by pulling the sda line low for one clock cycle after the address byte. after detecting the acknowledgement bit (a), the microprocessor transmits the second byte or command code. the command code identifies the type of write word protocol as setup, on or off (table 2). the setup protocol is used to load two resistor divider settings into register 0 and 1. the on and off protocols turn the converters on or off in conjunction with the vron pin. once all 8 bits of the command code are clocked in, the ltc1699-80, ltc1699-81 or ltc1699-82 issues a sec- ond acknowledgement bit to the microprocessor. after detecting the acknowledgement bit, the microprocessor transmits two data bytes. each data byte is acknowledged in turn for all three write word protocols but is only latched into register 0 or 1 in setup protocol. this prevents previously loaded settings from accidentally being changed. the first or data low byte is loaded into register 0. the second or data high byte is loaded into s 1110001 000xxxxx a don? care a don? care update dcon slave address on command data low (register 0) data high (register 1) a p s 1110001 011xxxxx a don? care a don? care update dcon slave address off command data low (register 0) data high (register 1) a p s 1110001 001xxxxx a vid4 vid3 vid2 vid1 vid0 x x x a a a a update dcon slave address setup command data high (register 1) data low (register 0) a p data low latched data high latched command latched vid4 vid3 vid2 vid1 vid0 x x x s 1110001 r/w r/w r/w r/w s 1110010 010xxxxx a vid4 vid3 vid2 vid1 vid0 0 0 rd a a a slave address read-back command data high (register 1) data low (register 0) a p data high loaded data low loaded stop (ignored) command latched dcon 00 dcon vid4 vid3 vid2 vid1 vid0 figure 2. write word and read word protocols
ltc1699 series 13 applicatio s i for atio wu u u register 1. after issuing the final acknowledgement bit, the smbus interface returns to an idle state and waits for the next start bit. read word protocol the read word protocol starts off like write word proto- col but after the command code acknowledgment, the microprocessor issues a second start bit (called a re- peated start). this is followed by the slave address but with the r/w bit set high to indicate that data direction is now from the ltc1699-80, ltc1699-81 or ltc1699-82 to the microprocessor. the ltc1699-80, ltc1699-81 or ltc1699-82 then acknowledges the slave address and clocks the contents of register 0 (data low byte) to the microprocessor. the data low byte is acknowledged by the microprocessor. on detecting the acknowledgment bit, the ltc1699-80, ltc1699-81 or ltc1699-82 clocks out the contents of register 1 (data high byte). as defined in the smbus specifications, the microprocessor does not acknowledge the last data byte. the ltc1699-80, ltc1699-81 or ltc1699-82 enters an idle state to wait for the next start bit after clocking out the data high byte. the five most significant bits (vid0-vid4) of the data low and high bytes are the resistor divider settings previously loaded using the setup protocol. the next bit below the vid0-vid4 bits is the status of the dcon signal. if this bit is low (high), the dc/dc converters are switched on (off). the two unused, least significant bits of the data low and data high bytes are clocked out as zeros which removes the need to mask out these bits in software. safeguards the ltc1699-80, ltc1699-81 and ltc1699-82 provide safeguards against incorrect divider codes and the unin- tentional turn-on or turn-off of the dc/dc converters. incorrect codes due to bus conflicts during setup proto- cols can cause damage to circuits powered by the dc/dc converters. the safeguards built into the ltc1699-80, ltc1699-81 and ltc1699-82 include read-back, re- peated on and off protocols, ignoring on protocols if the registers have not been setup, locking out registers while the dc/dc converters are operating and latching in vid codes only in setup protocols. after power-up, the microprocessor must set up the registers before the ltc1699-80, ltc1699-81 and ltc1699-82 recognizes on protocols. this requirement ensures that the correct dc/dc converter output is pro- grammed before the converters are turned on. after setup, read-back allows the contents of registers 0 and 1 to be verified in case the vid codes were corrupted by noise or bus conflicts. in order to turn on the dc/dc converter, two on protocols must be sent to slave address e2h without any other (e2h) protocols in between. protocols to other slave addresses are still allowed and are ignored. similarly, two off proto- cols must be sent to slave address e2h to turn the converters off. the on and off protocols are monitored by an internal state machine. the output of the state machine, smbon, is high after two on commands and low after two off commands. repeated on and off protocols reduce the chances of bus conflicts and noise turning the converter on or off accidentally. in both on and off protocols, the ltc1699-80, ltc1699-81 and ltc1699-82, do not latch in the data low and data high bytes. this protects the settings that have already been loaded into the registers and verified by read-back. once the converters are turned on (both smbon and vron are high) the contents of registers 0 and 1 are protected and can only be altered with setup protocols if vron is pulled low or two off protocols are sent to the ltc1699-80, ltc1699-81 or ltc1699-82 (to force smbon low). dc/dc converter control the ltc1699-80, ltc1699-81 and ltc1699-82 provide six pins for dc/dc converter control: sel, vron, cpu_on, io_on, clk_on and pgood. these pins (except sel) and the output of the internal on/off state machine (smbon) determine if the dc/dc converters are operating or in shutdown. the sel and vron pins are ttl compatible, high imped- ance inputs with a logic threshold of 1.3v over the entire 2.7v to 5.5v supply range. they are compatible with 3.3v logic and have 50mv of hysterisis for noise rejection. when pulled high or low, the sel pin selects register 1 and 0 respectively as the active divider setting. the vron
ltc1699 series 14 pin is used to shut down the converters without the need for lengthy smbus off protocols and can also be used to turn on up to three dc/dc converters simultaneously. the vron pin has an internal 2.5ua current source pull-up. the cpu_on, io_on and clk_on pins are n-channel, open drain outputs. these outputs can be connected to the run/ss pin of ltc dc/dc converters that generate the v cc supplies of the cpu, i/o circuits and the clock buffer. the run/ss pin shuts down the converter if pulled low and also serves as a connection for the soft-start capaci- tor. the cpu_on, io_on and clk_on pins are open drain outputs and do not interfere with soft-start when switched into a high impedance state. to keep the i/o and clock buffer v cc supplies alive at all times, disconnect the io_on and clk_on pins from the corresponding run/ss pins. the n-channel fets at the cpu_on, io_on and clk_on pins typically discharge a 0.1 m f (0.01 m f) soft-start capaci- tor from 3v to 0.35v in 21 m s (2.3 m s) with v cc = 2.7v. the pgood or power good pin is also an open drain, n-channel output. the pgood pin pulls low if the dc/dc converters are shutdown. if the converters are turned on, an internal timer keeps pgood low for 50 m s (typical) which allows time for the converters to enter regulation. toggling the sel pin while the converters are turned on also causes the pgood pin to pull low for 50 m s. the pgood pin may be used to force continuous operation in an ltc dc/dc converter. if the sel pin is toggled to select a lower output voltage, it may take an unacceptably long time for the output of the dc/dc converter to decrease to the new voltage under light load conditions. to reduce this time needed, the pgood pin can be connected to the fcb (force continuous bar) pin of the converter. when the sel pin is toggled to select a new code, fcb pin is forced low for 50 m s. this forces the dc/dc converter out of burst mode tm operation and into continuous mode. the vron pin and smbon, the output of the internal on/ off state machine, control the state of the cpu_on, io_on, clk_on and pgood pins. the dcon signal is a logical nand function of the logical states of vron and smbon and is the status bit that is returned during read-back. table 3 shows the state of the cpu_on, io_on, and clk_on pins for various combinations of vron and smbon. table 3. dc/dc converter control pins vron smbon dcon pgood cpu_on, io_on, clk_on 0x10 0 (note 3) 1010 0 1 - 0 for 50 m s z (note 2) (note 1) - 1 0 for 50 m s z (note 2) (note 1) note 1: also triggered by sel pin toggling. note 2: z = high impedance note 3: x = dont care if the dcon control bit goes high, the n-channel transistor at the cpu_on, io_on, clk_on and pgood pins turn on, pulling these pins to ground. any connected run/ss pins are pulled to ground, shutting down the converters. if the dcon control bit goes low, the n-channel transistor at the cpu_on, clk_on, io_on and pgood pins turn off and become high impedance outputs. this allows the soft- start capacitor at each run/ss pin to charge up and the dc/dc converters wake up gradually with a soft-start cycle. the pgood pin also pulls low for typically 50 m s to indicate that the converter outputs are temporarily out of regulation. an internal timer determines the duration of the low pulse. the timer is triggered by sel toggling or dcon going low. power-up reset on power-up, the internal por circuit generates a low reset pulse, which stays low until v cc rises above approxi- mately 2.2v. the reset pulse forces the smbus interface into an idle state in which it listens for a start bit. at the same time the outputs of both register 0 and register 1 are set to 11111b. the dcon bit is pulled high so that the cpu_on, io_on, clk_on and pgood pins are pulled low to shut down the dc/dc converters. applicatio s i for atio wu u u burst mode is a trademark of linear technology corporation.
ltc1699 series 15 applicatio s i for atio wu u u operating sequence a typical control sequence for the ltc1699-80, ltc1699-81 and ltc1699-82 is as follows: ? on power up, the dcon bit is preset to a high state by the power-on reset (por) circuit. the cpu_on, io_on and clk_on pins are pulled low to shut down the dc/ dc converters. pgood pulls low to indicate that the converters are not in regulation. ? pull vron low as a precaution. take sel high or low to select the divider setting; e.g., one that suits the existing power source (battery or wall-pack). ? use the setup protocol to load the appropriate divider settings in registers 0 and 1 and enable the on/off state machine. ? use the read-back protocol to verify the contents of registers 0 and 1. ? repeat the setup and read-back if the codes are incor- rect (due to bus conflicts). ? send two on protocols in succession to clear the dcon bit. ? use the read-back protocol to verify that the dcon is low. a high state will indicate that an on command code was corrupted by bus conflicts. ? pull vron high. since dcon = 0, the cpu_on, io_on and clk_on pins enter a high impedance state, allow- ing the dc/dc converters to soft-start. pgood stays low for 50 m s. ? to shut down the supply, send two off protocols to set the dcon bit high or pull vron low if immediate shutdown is required. the vron signal in the 8-pin msop versions of the ltc1699-80, ltc1699-81 and ltc1699-82 are pulled high internally by a 2.5 m a current source. for these versions, the converters are turned on or off only through the smbus interface. overvoltage protection faults toggling the sel pin, i.e. changing the ladder setting on the fly can trigger some converters with over-voltage fault protection (ovp) into a fault state if the new setting calls for a lower output voltage. for some converters such as the ltc1702, cycling the power supply is the only way to clear the fault and restore normal operation. for the ltc1702, an ovp fault is triggered if the difference between the programmed and prevailing output voltages is greater than 15%, and persists for more than 25 m s. to prevent the ovp fault from disabling the ltc1702, tie the fault pin of the ltc1702 low. tying fault low does not disable the ovp circuit but blocks its effects.
ltc1699 series 16 typical applicatio s u ltc1702 pv cc boost1 bg1 tg1 sw1 i max1 pgood1 fcb run/ss1 comp1 sgnd fb1 i max2 boost2 bg2 tg2 sw2 pgnd pgood2 fault run/ss2 comp2 fb2 v cc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 1 f 10 1 f 1 f 18.7k 20k 1k 100k 1699 ta02 v in 10k c out1 180 f 4v 6 15pf 220pf 220pf 100k 1 f v out1 0.9v to 2v at 15a 0.22 f q1 q3 q2 d3 d2 c out1 , c out2 : panasonic eefue0g181r c in : kemet ts10x157m010as d1, d2: motorola mbr0520lt1 d3: motorola mbrs320t3 l1: murata lqt12535c1r5n12 l2: coiltronics up2b-2r2 q1, q2, q3: international rectifier irf7811 q4, q5: 1/2 fairchild nds8926 d1 pwrgd1 l1 1 h + 10 f 1 f v in = 5v 10% 0.22 f c in 150 f 10v 2 + q5 q4 2200pf 15pf 220pf 10.2k 0.1% 11.5k 0.1% 10k l2 2.2 h c out2 180 f 4v 1 f v out2 1.5v/3a pwrgd2 + v in 10k to p fb clk_on io_on pgood vron sda sel scl v cc sense gnd ltc1699-80 cpu_on 0.1 f smbus programmed dual output mobile pentium processor supply
ltc1699 series 17 typical applicatio s u c16 0.47 f c3, c4: os-con ps680m c18?21: t510e108m004 l1, l2: sumida cep149-1r0mc q1?8: fds6670a or fds7760a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 c17 1000pf nc tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 ampmd run/ss sense1 + sense1 eain pllfltr pllin nc i th sgnd v diffout v os v os + sense2 sense2 + u1 ltc1929 q8 q7 q6 q5 q4 l1 1 h r4 0.002 q3 q2 q1 c12 1 f c13 2.2 f c8 0.47 f d1 bat54a v in + v in 5v c22 1 f c23 1 f + c3 c2 1 f c1, 1000pf + c4 12 c14 10 f l2 2 h r8 0.002 r1 10 v in + 1699 ta06 + c18 r9 50 + c19 + c20 + c21 c24 10 f v out + v out v osense + v osense 1.6v/40a remote sense r10 50 r3 10k c7 0.1 f r2 2.7k c9, 0.01 f c10, 100pf c11, 1nf c15 180pf r5, 10k u2 ltc1699-81 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sel nc sda scl vron pgood nc cpu_on sel sda scl vron pgood v cc gnd gnd fb sense nc clk_on io_on r11, 100k r6, 100k c25 0.1 f smbus controlled 5v input, 1.6v/40a cpu power supply
ltc1699 series 18 typical applicatio s u 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th pgood sense sense + v osense sgnd tg boost sw v in intv cc bg pgnd extv cc ltc1735-1 c ss 0.1 f c b 0.22 f c c2 220pf 47pf 100k 470k intv cc c c 220pf r c 20k 100k* *optional to defeat overcurrent latchoff r sense 0.004 v out 1.6v 12a 1000pf c osc 39pf + 4.7 f 1 f + c out 180 f 4v 3 c o 47 f 10v c in 150 f 6.3v 2 q1 fds6680a q2, q3 fds6680a 2 c out : panasonic eefueog181r c in : panasonic eefueoj151r c o : taiyo yuden lmk550bj476mm-b l1: coilcraft 1705022p-781hc q4, q5: 2n2222 r sense : irc lrf 2512-01-r004-j 1699 ta03 d b mbr0530 mbrd835l v in 5v l1 0.78 h v in 5v sgnd q4 q5 power good 10k fb pgood clk_on io_on cpu_on vron sda sel scl v cc sense to p gnd sgnd ltc1699-81 180pf 0.1 f smbus programmed cpu core voltage regulator for 2-step applications (v in = 5v) with burst mode operation disabled
ltc1699 series 19 package descriptio u dimensions in inches (millimeters) unless otherwise noted. gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660) gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.009 (0.229) ref msop (ms8) 1100 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" (0.152mm) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.043 (1.10) max 0.009 ?0.015 (0.22 ?0.38) 0.005 0.002 (0.13 0.05) 0.034 (0.86) ref 0.0256 (0.65) bsc 12 3 4 0.193 0.006 (4.90 0.15) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc1699 series 20 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2001 1699f lt/tp 0201 4k ? printed in usa related parts typical applicatio u part number description comments ltc1628/ high efficiency, 2-phase, synchronous step down switching regulators dual controller, 0.8v reference, wide input voltage range ltc1628-pg ltc1694/ smbus/i 2 c accelerators in sot-23 improves smbus/i 2 c data integrity ltc1694-1 ltc1702 dual 1 mhz synchronous 5v to 2.xv/1.xv switching regulator controller low input voltages, high efficiency ltc1735/ high efficiency synchronous step down switching regulators 0.8v reference, wide input voltage range, synchronizable/ ltc1735-1 programmable fixed frequency ltc1878 monolithic synchronous step down switching regulator 0.8v reference, internal synchronous switch, 2.65v v in 6v ltc1706-19 vid voltage programmer parallel interface, designed for 1.19v referenced switching regulators ltc1706-81 5-bit desktop vid programmer parallel interface, 0.8v reference intel desktop vid codes (vrm8.4) ltc1706-82 vid programmer for intel vrm9.0 parallel interface, 0.8v reference intel desktop vid codes (vrm9.0) ltc1778 wide operating range, no r sense tm step-down controller 2% to 90% duty cycle at 200khz, t on(min) 100ns, stable with ceramic c out ltc1929/ 2-phase high efficiency synchronous step-down switching regulators 2-phase single output controller, wide v in range: 4v to 36v ltc1929-pg operation no r sense is a trademark of linear technology corporation. v cc fb gnd sense scl sel pgood sda 8 6 7 5 3 1 4 2 p ltc1699 smbus1 smbus2 v cc gnd 5 4 1 2 ltc1694 0.1 f v cc to dc/dc converter smbus 1699 ta04 0.1 f enhanced data transmission speed

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